RIFFA - Reusable Integration Framework for FPGA Accelerators


I have been fortunate to work with Matt Jacobsen on RIFFA. RIFFA (Reusable Integration Framework for FPGA Accelerators) is a simple framework for communicating data from a host CPU to a FPGA via a PCI Express bus. The framework requires a PCIe enabled workstation and a FPGA on a board with a PCIe connector. RIFFA supports Windows and Linux, Altera and Xilinx, with bindings for C/C++, Python, MATLAB and Java. RIFFA supports Linux and Windows operating systems, as well as all currently available Xilinx and Altera development boards. It can also be used on Lattice development boards with little-or-no modifications, though we haven't tested it.

Since 2012, I have contributed on RIFFA 2.1, and developed RIFFA 2.2. RIFFA prior to 2.1 was released under a modified BSD license, and RIFFA 2.2 is now covered by a 3-Clause BSD license. You can track our development on github, or join the discussion on our users google group, or contribute on the developers google group. The high level architecture diagram for RIFFA 2.1 is at right.



Trellis - Toward a unified communication framework


Field Programmable Gate Arrays are being increasingly adopted for high performance systems in a wide range of fields and applications. Bioinformatics,  Genomics,  Computer Vision,  and Networking are commonly cited as the fastest growing application areas. However,  these systems often take many man-years to develop,  and as a result lag behind the development of algorithms and new technologies. We are creating a set of tools for application engineers that will facilitate development,  such as standard interfaces to high bandwidth peripherals,  memory architecture and network generators,  and FPGA to GPU communication drivers that can be used with emerging industry tools to facilitate turn-around-times and reduce the need for domain specialists. These tools will also enable FPGA's in more exotic high performance systems,  such as GPU-FPGA supercomputers,  expanding an already growing field of FPGA development.

The high-level diagram of the Trellis-PCIe stack is on the left.

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